Detailed information about the SystemC TLM2 Fast Processor Model of the Renesas V850E1 core.
Processor IP owner is Renesas (formerly NEC). More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model has been run through an extensive QA and regression testing process.

Overview of Fast Processor Model
Model Variant name: V850E1
Description:
    V850 Family Processor Model.
Licensing:
    Open Source Apache 2.0
Limitations:
    The following Debug Registers are non-functional DIR, BPC0, BPC1, ASID BPAV0, BPAV1, BPAM0, BPAM1 BPDV0, BPDV1, BPDM0, BPDM1
Verification:
    Models have been extensively tested by Imperas, In addition Verification suites have been supplied by Renesas for CORE validation
Features:
    All v850e1 Instructions are supported.
    All Program and System Registers are supported.

Model downloadable (needs registration and to be logged in) in package v850.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant V850E1 is available OVP_Model_Specific_Information_v850_V850E1.pdf.

Configuration
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: renesas.ovpworld.org/processor/v850/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0x57

TLM Initiator Ports (Bus Ports)
Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32
SystemC Signal Ports (Net Ports)
Port TypeNameDescription
intpinputInterrupt Port
nmi0inputNon-Maskable Interrupt Port
nmi1inputNon-Maskable Interrupt Port
nmi2inputNon-Maskable Interrupt Port
resetinputReset Port
miretioutputReturn from Interrupt Port
intackoutputInterrupt Acknowledge Port

No FIFO Ports in V850E1.

Exceptions
NameCodeDescription
reset0Reset Signal Exception
nmi016Non Maskable Interrupt(0) Exception
nmi132Non Maskable Interrupt(1) Exception
nmi248Non Maskable Interrupt(2) Exception
intp65535Maskable Interrupt Exception - Vector value = (0x0000ffff AND intp)
trap064TRAP0 Exception
trap180TRAP1 Exception
ilgop96Illegal OPCODE Exception

No Execution Modes in V850E1.

More Detailed Information

The V850E1 SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_v850_V850E1.pdf.

Other Sites/Pages with similar information

Information on the V850E1 OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/renesas_models/v850e1
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/renesas_models/v850e1
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/renesas_models/v850e1
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/renesas_models/v850e1
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/renesas_models/v850e1


Currently available Fast Processor Model Families.

FamilyModel Variant
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R m16c r8c (aliases)
POWER Models    POWER Models aliases powerpc32 powerpc32uisa powerpc32vea powerpc32oea (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 ARMv7-M Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP interAptiv proAptiv 5Kf 5Kc 5KEf 5KEc (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores OR1K_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_ISA (aliases)