|Port Type||Name||Width (bits)||Description|
Detailed information about the SystemC TLM2 Fast Processor Model of the Renesas V850E1 core.
Processor IP owner is Renesas (formerly NEC). More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model has been run through an extensive QA and regression testing process.
Model downloadable (needs registration and to be logged in) in package v850.model for Windows32 and for Linux32
Model Variant name: V850E1
V850 Family Processor Model.
Open Source Apache 2.0
The following Debug Registers are non-functional DIR, BPC0, BPC1, ASID BPAV0, BPAV1, BPAM0, BPAM1 BPDV0, BPDV1, BPDM0, BPDM1
Models have been extensively tested by Imperas, In addition Verification suites have been supplied by Renesas for CORE validation
All v850e1 Instructions are supported.
All Program and System Registers are supported.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant V850E1 is available OVP_Model_Specific_Information_v850_V850E1.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: renesas.ovpworld.org/processor/v850/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0x57
|nmi0||input||Non-Maskable Interrupt Port|
|nmi1||input||Non-Maskable Interrupt Port|
|nmi2||input||Non-Maskable Interrupt Port|
|mireti||output||Return from Interrupt Port|
|intack||output||Interrupt Acknowledge Port|
|reset||0||Reset Signal Exception|
|nmi0||16||Non Maskable Interrupt(0) Exception|
|nmi1||32||Non Maskable Interrupt(1) Exception|
|nmi2||48||Non Maskable Interrupt(2) Exception|
|intp||65535||Maskable Interrupt Exception - Vector value = (0x0000ffff AND intp)|
|ilgop||96||Illegal OPCODE Exception|
The V850E1 SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_v850_V850E1.pdf.
Information on the V850E1 OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/renesas_models/v850e1
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/renesas_models/v850e1
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/renesas_models/v850e1
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/renesas_models/v850e1
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/renesas_models/v850e1
Currently available Fast Processor Model Families.