| Port Type | Name | Width (bits) | Description |
|---|---|---|---|
| master | INSTRUCTION | 32 | |
| master | DATA | 32 |
Detailed information about the SystemC TLM2 Fast Processor Model of the Renesas m16c core.
Processor IP owner is Renesas (formerly Mitsubishi). More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model has been run through an extensive QA and regression testing process.
Model Variant name: m16c
Description:
M16c Family 16Bit CISC processor model.
Licensing:
Copyright Posedge Software, Licensed as Open Source Apache 2.0
Limitations:
Core Instruction Set Architecture only.
Interrupt and Reset Signals are TBD.
Verification:
Model has been validated correct by running through extensive instruction level tests
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant m16c is available OVP_Model_Specific_Information_m16c_m16c.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: posedgesoft.ovpworld.org/processor/m16c/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0x75
| Port Type | Name | Description |
|---|---|---|
| reset | input | |
| nmi | input | |
| int_per | input | |
| int_ack | output |
| Name | Code | Description |
|---|---|---|
| Undefined | 0 | |
| Overflow | 1 | |
| BRK | 2 | |
| AddressMatch | 3 | |
| SingleStep | 4 | |
| Watchdog | 5 | |
| DBC | 6 | |
| NMI | 7 | |
| Reset | 8 | |
| Fetch | 9 |
The m16c SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_m16c_m16c.pdf.
Information on the m16c OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/renesas_models/m16c
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/renesas_models/m16c
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/renesas_models/m16c
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/renesas_models/m16c
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/renesas_models/m16c
Currently available Fast Processor Model Families.