Detailed information about the SystemC TLM2 Fast Processor Model of the MIPS 1074k (1074Kc) core.
This page is information about the 1074k alias of the 1074Kc variant.
Processor IP owner is MIPS Technologies. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model has been run through an extensive QA and regression testing process.

Overview of Fast Processor Model
Model Variant name: 1074k (1074Kc)
Description:
    MIPS32 Configurable Processor Model
Licensing:
    Open Source Apache 2.0
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    MIPS32 Instruction set implemented
    MMU Type: Standard TLB
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Vectored interrupts implemented
    MIPS16e ASE implemented
    DSP ASE Rev 2 implemented

Model downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant 1074k (1074Kc) is available OVP_Model_Specific_Information_mips32_1074Kc.pdf.

Configuration
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8

TLM Initiator Ports (Bus Ports)
Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32
SystemC Signal Ports (Net Ports)
Port TypeNameDescription
resetinputCMP reset
dintinputDebug external interrupt
int0inputGIC external interrupt
int1inputGIC external interrupt
int2inputGIC external interrupt
int3inputGIC external interrupt
int4inputGIC external interrupt
int5inputGIC external interrupt
int6inputGIC external interrupt
int7inputGIC external interrupt
int8inputGIC external interrupt
int9inputGIC external interrupt
int10inputGIC external interrupt
int11inputGIC external interrupt
int12inputGIC external interrupt
int13inputGIC external interrupt
int14inputGIC external interrupt
int15inputGIC external interrupt
int16inputGIC external interrupt
int17inputGIC external interrupt
int18inputGIC external interrupt
int19inputGIC external interrupt
int20inputGIC external interrupt
int21inputGIC external interrupt
int22inputGIC external interrupt
int23inputGIC external interrupt
int24inputGIC external interrupt
int25inputGIC external interrupt
int26inputGIC external interrupt
int27inputGIC external interrupt
int28inputGIC external interrupt
int29inputGIC external interrupt
int30inputGIC external interrupt
int31inputGIC external interrupt
int32inputGIC external interrupt
int33inputGIC external interrupt
int34inputGIC external interrupt
int35inputGIC external interrupt
int36inputGIC external interrupt
int37inputGIC external interrupt
int38inputGIC external interrupt
int39inputGIC external interrupt
reset_CPU0inputCore reset
hwint0_CPU0inputExternal interrupt
hwint1_CPU0inputExternal interrupt
hwint2_CPU0inputExternal interrupt
hwint3_CPU0inputExternal interrupt
hwint4_CPU0inputExternal interrupt
hwint5_CPU0inputExternal interrupt
nmi_CPU0inputNon-maskable external interrupt
hwint0inputExternal interrupt for compatibility
reset_CPU1inputCore reset
hwint0_CPU1inputExternal interrupt
hwint1_CPU1inputExternal interrupt
hwint2_CPU1inputExternal interrupt
hwint3_CPU1inputExternal interrupt
hwint4_CPU1inputExternal interrupt
hwint5_CPU1inputExternal interrupt
nmi_CPU1inputNon-maskable external interrupt
reset_CPU2inputCore reset
hwint0_CPU2inputExternal interrupt
hwint1_CPU2inputExternal interrupt
hwint2_CPU2inputExternal interrupt
hwint3_CPU2inputExternal interrupt
hwint4_CPU2inputExternal interrupt
hwint5_CPU2inputExternal interrupt
nmi_CPU2inputNon-maskable external interrupt
reset_CPU3inputCore reset
hwint0_CPU3inputExternal interrupt
hwint1_CPU3inputExternal interrupt
hwint2_CPU3inputExternal interrupt
hwint3_CPU3inputExternal interrupt
hwint4_CPU3inputExternal interrupt
hwint5_CPU3inputExternal interrupt
nmi_CPU3inputNon-maskable external interrupt

No FIFO Ports in 1074k.

Exceptions
NameCodeDescription
Int0
Mod1
TLBL2
TLBS3
AdEL4
AdES5
IBE6
DBE7
Sys8
Bp9
RI10
CpU11
Ov12
Tr13
FPE15
Impl116
Impl217
C2E18
TLBRI19
TLBXI20
MDMX22
WATCH23
MCheck24
Thread25
DSPDis26
Prot29
CacheErr30
Execution Modes
ModeCodeDescription
KERNEL0
DEBUG1
SUPERVISOR2
USER3
More Detailed Information

The 1074k SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_1074Kc.pdf.

Other Sites/Pages with similar information

Information on the 1074k OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/mips_models_aliases/1074k
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/mips_models_aliases/1074k
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/mips_models_aliases/1074k
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/mips_models_aliases/1074k
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/mips_models_aliases/1074k


Currently available Fast Processor Model Families.

FamilyModel Variant
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R m16c r8c (aliases)
POWER Models    POWER Models aliases powerpc32 powerpc32uisa powerpc32vea powerpc32oea (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 ARMv7-M Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP interAptiv proAptiv 5Kf 5Kc 5KEf 5KEc (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores OR1K_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_ISA (aliases)