Using SystemC TLM2 processor models.

It is very easy to use the Fast Processor Models in SystemC TLM2 platforms.

An OVP Fast Processor Model is provided with a TLM2 interface in the form of a  C++ header file. This is then included in the TLM2 platform source. It defines a SystemC module class specific to the processor type which can be instantiated in your platform. This class is derived from a generic interface, icmCPU (itself derived from sc_module). (OVP peripherals are instantiated in the same way.)

An Example Platform:

TLM2 Single Core Platform

Each processor model is run from a SystemC thread. The thread executes InstructionsPerQuanta instructions on the processor without advancing SystemC time. Each instruction may or may not cause TLM2 transactions to be propagated to other components in the platform. When the allotted instructions have completed, the thread calls SystemC wait()to advance time. The SystemC scheduler will move time forward outside of these quantum executions. Thus each processor in a multi-processor simulation executes a number of instructions at a time in a round-robin schedule.

TLM2 allows comprehensive modeling of  bus transactions, but each transaction adds a  significant time overhead in the context of an instruction-accurate simulation. Direct Memory Interface (DMI) allows negotiation between two TLM2 models so that an initiator can directly access target memory, bypassing the TLM2 mechanism.

An OVP Fast Processor Model uses DMI negotiation by default. In practice, a processor with a fixed program memory will execute one code-fetch via TLM2. The DMI hint in that transaction will allow the simulator to map the program memory into its address space so that subsequent code-fetches do not use TLM2 transactions. DMI can be disabled with an optional argument to the model constructor.

For more information and specifics with worked through examples, download the user guide. (OVP registration and login required.)

Currently available Fast Processor Model Families.

FamilyModel Variant
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R m16c r8c (aliases)
POWER Models    POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 ARMv7-M Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP interAptiv proAptiv 5Kf 5Kc 5KEf 5KEc (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)