Cortex-A5UP | SystemC Models

Detailed information about the SystemC TLM2 Fast Processor Model of the ARM Cortex-A5UP core.
Processor IP owner is ARM Holdings. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model has been run through an extensive QA and regression testing process.

Overview of Fast Processor Model
Model Variant name: Cortex-A5UP
Description:
    ARM Processor Model
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    Performance Monitors are implemented as a register interface only.
Verification:
    Models have been extensively tested by Imperas. All functional blocks of ARM Cortex-A5 models have been extensively tested by Imperas. The configuration of the ARM Cortex-A5 models have not been verified. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desk
Features:
    MMU is implemented.
    Thumb-2 instructions are supported.
    Trivial Jazelle extension is implemented.
    SIMD instructions are implemented.
    NEON is implemented.
    VFP is implemented.
    Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.

Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant Cortex-A5UP is available OVP_Model_Specific_Information_arm_Cortex-A5UP.pdf.

Configuration
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28

TLM Initiator Ports (Bus Ports)

Port Type	Name	Width (bits)	Description
master	INSTRUCTION	32
master	DATA	32

SystemC Signal Ports (Net Ports)

Port Type	Name	Description
fiq	input	Fast external interrupt (active high)
irq	input	External interrupt (active high)
reset	input	Processor reset (active high)
CP15SDISABLE	input	CP15SDISABLE (active high)

No FIFO Ports in Cortex-A5UP.

Exceptions

Name	Code	Description
Reset	0
Undefined	1
SupervisorCall	2
SecureMonitorCall	3
PrefetchAbort	5
DataAbort	6
IRQ	8
FIQ	9

Execution Modes

Mode	Code	Description
User	16
FIQ	17
IRQ	18
Supervisor	19
Monitor	22
Abort	23
Undefined	27
System	31

More Detailed Information

The Cortex-A5UP SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_Cortex-A5UP.pdf.

Other Sites/Pages with similar information

Information on the Cortex-A5UP OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/arm_models/cortex-a5up
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/arm_models/cortex-a5up
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/arm_models/cortex-a5up
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/arm_models/cortex-a5up
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/arm_models/cortex-a5up

Currently available Fast Processor Model Families.

Family	Model Variant
Renesas Models	Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R m16c r8c (aliases)
POWER Models	POWER Models aliases powerpc32 powerpc32uisa powerpc32vea powerpc32oea (aliases)
ARM Models	ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 ARMv7-M Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
MIPS Models	MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP interAptiv proAptiv 5Kf 5Kc 5KEf 5KEc (aliases)
Other Models	Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores OR1K_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_ISA (aliases)