| Port Type | Name | Width (bits) | Description |
|---|---|---|---|
| master | INSTRUCTION | 32 | |
| master | DATA | 32 |
Detailed information about the SystemC TLM2 Fast Processor Model of the ARM ARMv5TE core.
Processor IP owner is ARM Holdings. More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model has been run through an extensive QA and regression testing process.
Model Variant name: ARMv5TE
Description:
ARM Processor Model
Licensing:
Imperas Modified Apache 2.0 Open Source License
Verification:
Models have been extensively tested by Imperas.
Features:
Thumb instructions are supported.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant ARMv5TE is available OVP_Model_Specific_Information_arm_ARMv5TE.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
| Port Type | Name | Description |
|---|---|---|
| fiq | input | Fast external interrupt (active high) |
| irq | input | External interrupt (active high) |
| reset | input | Processor reset (active high) |
| Name | Code | Description |
|---|---|---|
| Reset | 0 | |
| Undefined | 1 | |
| SupervisorCall | 2 | |
| PrefetchAbort | 5 | |
| DataAbort | 6 | |
| IRQ | 8 | |
| FIQ | 9 |
| Mode | Code | Description |
|---|---|---|
| User | 16 | |
| FIQ | 17 | |
| IRQ | 18 | |
| Supervisor | 19 | |
| Abort | 23 | |
| Undefined | 27 | |
| System | 31 |
The ARMv5TE SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_ARMv5TE.pdf.
Information on the ARMv5TE OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/arm_models/armv5te
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/arm_models/armv5te
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/arm_models/armv5te
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/arm_models/armv5te
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/arm_models/armv5te
Currently available Fast Processor Model Families.