|Port Type||Name||Width (bits)||Description|
Detailed information about the SystemC TLM2 Fast Processor Model of the ARM cortex-a5-mpcore (Cortex-A5MPx1) core.
This page is information about the cortex-a5-mpcore alias of the Cortex-A5MPx1 variant.
Processor IP owner is ARM Holdings. More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model has been run through an extensive QA and regression testing process.
Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
Model Variant name: cortex-a5-mpcore (Cortex-A5MPx1)
ARM Processor Model
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Performance Monitors are implemented as a register interface only.
Models have been extensively tested by Imperas. All functional blocks of ARM Cortex-A5 models have been extensively tested by Imperas. The configuration of the ARM Cortex-A5 models have not been verified. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desk
MMU is implemented.
Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.
SIMD instructions are implemented.
NEON is implemented.
VFP is implemented.
Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
MPCore block is implemented (GICv1, including security extensions).
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant cortex-a5-mpcore (Cortex-A5MPx1) is available OVP_Model_Specific_Information_arm_Cortex-A5MPx1.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
|SPI32||input||Shared peripheral interrupt|
|SPI33||input||Shared peripheral interrupt|
|SPI34||input||Shared peripheral interrupt|
|SPI35||input||Shared peripheral interrupt|
|SPI36||input||Shared peripheral interrupt|
|SPI37||input||Shared peripheral interrupt|
|SPI38||input||Shared peripheral interrupt|
|SPI39||input||Shared peripheral interrupt|
|SPI40||input||Shared peripheral interrupt|
|SPI41||input||Shared peripheral interrupt|
|SPI42||input||Shared peripheral interrupt|
|SPI43||input||Shared peripheral interrupt|
|SPI44||input||Shared peripheral interrupt|
|SPI45||input||Shared peripheral interrupt|
|SPI46||input||Shared peripheral interrupt|
|SPI47||input||Shared peripheral interrupt|
|SPI48||input||Shared peripheral interrupt|
|SPI49||input||Shared peripheral interrupt|
|SPI50||input||Shared peripheral interrupt|
|SPI51||input||Shared peripheral interrupt|
|SPI52||input||Shared peripheral interrupt|
|SPI53||input||Shared peripheral interrupt|
|SPI54||input||Shared peripheral interrupt|
|SPI55||input||Shared peripheral interrupt|
|SPI56||input||Shared peripheral interrupt|
|SPI57||input||Shared peripheral interrupt|
|SPI58||input||Shared peripheral interrupt|
|SPI59||input||Shared peripheral interrupt|
|SPI60||input||Shared peripheral interrupt|
|SPI61||input||Shared peripheral interrupt|
|SPI62||input||Shared peripheral interrupt|
|SPI63||input||Shared peripheral interrupt|
|SPI64||input||Shared peripheral interrupt|
|SPI65||input||Shared peripheral interrupt|
|SPI66||input||Shared peripheral interrupt|
|SPI67||input||Shared peripheral interrupt|
|SPI68||input||Shared peripheral interrupt|
|SPI69||input||Shared peripheral interrupt|
|SPI70||input||Shared peripheral interrupt|
|SPI71||input||Shared peripheral interrupt|
|SPI72||input||Shared peripheral interrupt|
|SPI73||input||Shared peripheral interrupt|
|SPI74||input||Shared peripheral interrupt|
|SPI75||input||Shared peripheral interrupt|
|SPI76||input||Shared peripheral interrupt|
|SPI77||input||Shared peripheral interrupt|
|SPI78||input||Shared peripheral interrupt|
|SPI79||input||Shared peripheral interrupt|
|SPI80||input||Shared peripheral interrupt|
|SPI81||input||Shared peripheral interrupt|
|SPI82||input||Shared peripheral interrupt|
|SPI83||input||Shared peripheral interrupt|
|SPI84||input||Shared peripheral interrupt|
|SPI85||input||Shared peripheral interrupt|
|SPI86||input||Shared peripheral interrupt|
|SPI87||input||Shared peripheral interrupt|
|SPI88||input||Shared peripheral interrupt|
|SPI89||input||Shared peripheral interrupt|
|SPI90||input||Shared peripheral interrupt|
|SPI91||input||Shared peripheral interrupt|
|SPI92||input||Shared peripheral interrupt|
|SPI93||input||Shared peripheral interrupt|
|SPI94||input||Shared peripheral interrupt|
|SPI95||input||Shared peripheral interrupt|
|SPIVector||input||Shared peripheral interrupt vectorized input|
|periphReset||input||Peripheral reset (active high)|
|wdResetReq_CPU0||output||Watchdog interrupt request|
|wdReset_CPU0||input||Watchdog reset (active high)|
|scuReset||input||SCU reset (active high)|
|fiq_CPU0||input||Fast external interrupt (active high)|
|irq_CPU0||input||External interrupt (active high)|
|reset_CPU0||input||Processor reset (active high)|
|CP15SDISABLE_CPU0||input||CP15SDISABLE (active high)|
The cortex-a5-mpcore SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_Cortex-A5MPx1.pdf.
Information on the cortex-a5-mpcore OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/arm_models_aliases/cortex-a5-mpcore
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/arm_models_aliases/cortex-a5-mpcore
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/arm_models_aliases/cortex-a5-mpcore
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/arm_models_aliases/cortex-a5-mpcore
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/arm_models_aliases/cortex-a5-mpcore
Currently available Fast Processor Model Families.