|Port Type||Name||Width (bits)||Description|
Detailed information about the SystemC TLM2 Fast Processor Model of the ARM arm (ARMv7) core.
This page is information about the arm alias of the ARMv7 variant.
Processor IP owner is ARM Holdings. More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model has been run through an extensive QA and regression testing process.
Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
Model Variant name: arm (ARMv7)
ARM Processor Model
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Models have been extensively tested by Imperas.
Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.
Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant arm (ARMv7) is available OVP_Model_Specific_Information_arm_ARMv7.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
|fiq||input||Fast external interrupt (active high)|
|irq||input||External interrupt (active high)|
|reset||input||Processor reset (active high)|
|CP15SDISABLE||input||CP15SDISABLE (active high)|
The arm SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_ARMv7.pdf.
Information on the arm OVP Fast Processor Model can also be found on other web sites:
www.systemc-cpu-models.org has the page www.systemc-cpu-models.org/arm_models_aliases/arm
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.systemc-processor-models.org has the page www.systemc-processor-models.org/arm_models_aliases/arm
www.systemc-tlm-cpu-models.org has the page www.systemc-tlm-cpu-models.org/arm_models_aliases/arm
www.systemc-tlm-models.org has the page www.systemc-tlm-models.org/arm_models_aliases/arm
www.systemc-tlm-processor-models.org has the page www.systemc-tlm-processor-models.org/arm_models_aliases/arm
Currently available Fast Processor Model Families.