This site provides information on the industry’s most comprehensive library of open source models of advanced processor cores that work in SystemC TLM2 environments.

You can download these models and use them in your own SystemC TLM2 platforms. They have been tested to run with all major SystemC simulators: Cadence, Synopsys, Mentor, Carbon, OSCI. The models have also been tested with Eve and Aldec. The models run on both Windows and Linux host platforms.

On this site you will see the scope and variety of the Fast Processor Models available and how easy they are to download and use in SystemC TLM2 simulations.

Each model is written in C using the Open Virtual Platforms (OVP) standard public APIs. They include a dedicated native C++ SystemC TLM2 interface provided as source to enable understanding and easy usage. Not only is the specific SystemC TLM2 interface provided as source (click to preview an example), also, the full model is available as open source. The models do require a simulator that implements the OVP APIs – such as OVPsim available from OVP, or commercial simulators from companies such as Imperas Software.

There is documentation that explains about the models in general (click to preview) and a specific document (click to preview an example) that describes what is available in the model, for example its ports, nets, registers, modes, exceptions, and other configuration/parameter options.

An overview document (click to preview) explains, with the use of examples, how the models are configured and used in SystemC TLM2 platforms.

The models operate just like any other SystemC TLM2 models with no inefficient co-simulation. It is very simple to create homogeneous or heterogenous platforms of advanced processor core models. To see examples of SystemC TLM2 platforms ranging from one to twenty-four cores and for platforms that boot full operating systems like Linux and Android, including SMP, visit the the examples and platforms available from the OVP TLM2 platforms download area or video area.

Many models can be instanced in one SystemC TLM2 platform, virtual platform or virtual system prototype – it is easy to build multi-core mult-processor platforms.

Each model supports standard debugging interfaces and can be connected using RSP to GDB, either standalone or within an Eclipse IDE environment.

The models run fast, hundreds of millions of instructions per second (MIPS):

SystemC TLM2 Fast Processor Models run fast

To see a short video of a Fast Processor Model running in a SystemC TLM2 platform – and see it booting to the Linux prompt in under 10 seconds, click the image:SystemC TLM2 Arm Integrator Linux Video
At the top of this page are several menu picks that list the different families and enable access to the model specific information. The listed items on the right provide more information.

Thank you for your interest – the Open Virtual Platforms Fast Processor Models team. To contact us please visit Imperas or OVP.

Currently available Fast Processor Model Families.

FamilyModel Variant
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
POWER Models    POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
RISC-V Models    RISC-V Models aliases RV32I RV32G RV64I RV64G RISCV_UISA (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)